1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. For example, the present invention relates to a structure of an element isolation region in a NAND flash memory having a MONOS structure.
2. Description of the Related Art
As a structure of a nonvolatile memory cell transistor in a semiconductor memory device, a conventional MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure is known. The MONOS structure has a structure which has an electric charge accumulating layer (for example, insulating film) formed on a semiconductor substrate through a gate insulating film, an insulating film (to be referred to as a block layer hereinafter) formed on the electric charge accumulating layer and having a dielectric constant higher than that of the electric charge accumulating layer, and a control gate electrode formed on the block layer. This is described on, for example, Pages 110 to 111 in “Self Aligned Trap-Shallow Trench Isolation Scheme For the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory”, by Jae Sung Sim, NVSMW, August 2007.
A semiconductor memory device has an element isolation region which electrically isolates an active region in which a nonvolatile memory cell transistor having a MONOS structure is arranged. An upper surface of the element isolation region is formed at a level higher than that of an upper surface of an electric charge accumulating layer formed on the active region to form a step on an upper surface of a block film formed on the active region and the element isolation region. For this reason, a distance from the upper surface of the control gate to the block layer on the active region is longer than a distance from the upper surface of the control gate on the element isolation region to the block layer. In this state, when a voltage is applied to the control gate, a voltage is not transmitted to the electric charge accumulating layer formed on the active region sufficiently. A higher voltage must be applied to control gate in the conventional structure, for example, to achieve 4 values (2 bits/cell) per cell.